1. Field of the Invention
The present invention relates to a method of fabricating a low temperature polysilicon thin film transistor liquid crystal display (LTPS TFT-LCD), and more particularly, to a method of fabricating a low temperature polysilicon thin film transistor liquid crystaldisplay with precise alignment and superior reliability by utilizingnine photo-etching-processes (PEPs).
2. Description of the Prior Art
Nowadays, a liquid crystal display (LCD) is the most mature flat panel display technique. The applications for a liquid crystal display are extensive and include mobile phones, digital cameras, video cameras, notebooks, and monitors. Due to the high quality vision requirements and the expansion of new application fields, the LCD has developed toward high quality, high resolution, high brightness, and low price. The low temperature polysilicon thin film transistor (LTPS-TFT), having a character of being actively driven, is a break-through in achieving the above objective. Therefore, the technological innovation based on this concept has become an important subject.
Please refer to FIG. 1 to FIG. 8 that are schematic diagrams of a method for forming a low temperature polysilicon thin film transistor liquid crystal display (LTPS TFT-LCD) according to a prior art. The prior art low temperature polysilicon thin film transistor liquid crystal display (LTPS TFT-LCD) 98 is formed on an insulation substrate 10. The insulation substrate 10, composed of transparent materials, may be a glass substrate or a quartz substrate. A pixel array area 11 and a periphery circuit area 13 are comprised on a surface of the insulation substrate 10.
An amorphous silicon thin film (Î±−Si thin film, not shown) is formed on the surface of the insulation substrate 10 first. Then an excimer laser annealing (ELA) process is performed to re-crystallize the amorphous silicon thin film (not shown) into a polysilicon layer (not shown). A first photo-etching-process (PEP-1) is thereafter performed to define an active area 12 in the pixel array area 11 and at least one active area 14 in the periphery circuit area 13. A source region (not shown), a drain region (not shown), a channel region (not shown), and a predetermined region for a bottom storage electrode (not shown) are comprised in the active area 12; a source region (not shown), a drain region (not shown), and a channel region (not shown) are comprised in each active area 14.
As shown in FIG. 2, a second photo-etching-process (PEP-2) is performed to form a photoreisist layer 16 on the top surface of the insulation substrate 10. The photoresist layer 16 is used to define the sites for the bottom storage electrode 18 in the pixel array area 11. After that, an ion implantation process is performed to dope high concentration N-type dopants into the exposed portion of the active area 12 in the pixel array area 11, completing the fabrication of the bottom storage electrode 18. The first photoresist layer 16 is then removed.
As shown in FIG. 3, an isolation layer 22 and a first conductive layer (not shown) are formed on the surface of the insulation substrate 10 sequentially.
Then a third photo-etching-process (PEP-3) is performed to simultaneously form a gate electrode 24 of a thin film transistor and a top storage electrode 26 on top of the bottom storage electrode 18 in the pixel array area 11, and a gate electrode 28 of an N-type metal-oxide-semiconductor (NMOS) and a gate electrode 32 of a P-type metal-oxide-semiconductor (PMOS), respectively, in the periphery circuit area 13.
As shown in FIG. 4, an etching process is performed, by utilizing the above mentioned gate electrode 24, the gate electrode 28, the gate electrode 32, and the top storage electrode 26 as etching masks, to remove portions of the isolation layer 22 to form the gate insulating layers 34, 36, 38, and the capacitor dielectric layer 42. The manufacturing of the storage capacitor 44 is thus completed.
After that, an ion implantation process, by utilizing the gate electrodes 24, 28, 32 as masks, is performed to dope low concentration N-type ions into the active areas 12, 14 at either side of the gate electrodes 24, 28, 32 to form the lightly doped drains 46, 48, 52. Due to the low concentration N-type ions implanted in this ion implantation process, the doping concentration of the bottom storage electrode 18 is not affected.
As shown in FIG. 5, a fourth photo-etching-process (PEP-4) is performed to form a photoresist layer 54 on the top surface of the insulation substrate 10. The photoresist layer 54 covers the gate electrode 24 and the predetermined region for a lightly doped drain 56 in the pixel array area 11 and simultaneously covers the predetermined region for a P-type metal-oxide-semiconductor in the periphery circuit area 13. An ion implantation process is thereafter performed to dope high concentration N-type ions to form a source electrode 62 and a drain electrode 64 of a thin film transistor 58 in the active area 12 in the pixel array area 11 and simultaneously form a source electrode 68 and a drain electrode 72 of an N-type metal-oxide-semiconductor 66 in the active area 14 in the periphery circuit area 13.
The photoresist layer 54 is removed. As shown in FIG. 6, a fifth photo-etching-process (PEP-5) is performed to form a photoresist layer 74 on the top surface of the insulation substrate 10. The photoresist layer 74 exposes the predetermined region for the P-type metal-oxide-semiconductor 76 in the periphery circuit area 13. After that, an ion implantation process is performed to dope high concentration P-type ions to form a source electrode 78 and a drain electrode 82 of the P-type metal-oxide-semiconductor 76 in the active area 14 in the periphery circuit area 13. Due to the high concentration P-type ions implanted in this ion implantation process, the previously formed N-type lightly doped drain 52 (shown in FIG. 5) is compensated and the source electrode 78 and the drain electrode 82 are thus formed. The photoresist layer 74 is then removed.
As shown in FIG. 7, an isolation layer 84 is formed on the surface of the insulation substrate 10. The isolation layer 84 covers the gate electrodes 24, 28, 32 and the top storage electrode 26. Then a sixth photo-etching-process (PEP-6) is performed to remove portions of the isolation layer 84 to form a plurality of contact holes 85. The contact holes 85 are electrically connected to the source electrodes 62, 68, 78 and the drain electrodes 72, 82, respectively. A source wire 86, electrically connected to the source electrode 62, is formed on top of the contact hole 85 in the pixel array area 11. Source wires 88, electrically connected to the source electrodes 68, 78 respectively, are formed on top of the contact holes 85 in the periphery circuit area 13. A wire 92 electrically connecting the N-type metal-oxide-semiconductor 66 to the P-type metal-oxide-semiconductor 76 is formed to complete the manufacturing of the complementary metal oxide semiconductor (CMOS).
As shown in FIG. 8, an isolation layer 94 is formed on the surface of the entire structure to cover the isolation layer 84, the source wires 86, 88, and the wire 92. A seventh photo-etching-process (PEP-7) is performed to remove portions of the third isolation layer 94 to form a contact hole 95. The contact hole 95 extends downward and is electrically connected to the drain electrode 64. A transparent conductive layer is thereafter formed on the isolation layer 94. Finally, an eighth photo-etching-process (PEP-8) is performed to remove portions of the transparent conductive layer to form a pixel electrode 96 on the isolation layer 94. The pixel electrode 96 is electrically connected to the drain electrode 64 downward though the contact hole 95 filled with the transparent conductive layer (not shown) to complete the fabrication of the low temperature polysilicon thin film transistor liquid crystal display 98.
However, the prior art method for forming the low temperature polysilicon thin film transistor liquid crystal display 98 results in a very severe problem. When forming the low storage electrode, the source electrode, the drain electrode, and the lightly doped drain according to the prior art method for forming the low temperature polysilicon thin film transistor liquid crystal display 98, three different photoresist layers and four different ion implantation processes are necessarily performed. When forming each photoresist layer, a photolithography process that tends to incur alignment error is required. After so many and complicated photolithography processes, defects are readily produced on the product. Especially the sum of the alignment error incurred from forming the gate electrode and the alignment errors incurred from forming the source electrode and the drain electrode of the thin film transistor in the pixel array area always results in the lightly doped drain having an uneven width. The asymmetric lightly doped drain cannot inhibit the hot electron effect. Moreover, an early breakdown of device is likely to happen. Therefore, it is very important to develop a method of forming a low temperature polysilicon thin film transistor liquid crystal display, so the manufacturing complexity is reduced and the number of photolithography processes is decreased to lower the probability of misalignment to improve the device defect problem and to ensure a certain production yield.